silicon photonics:

Intel/Barefoot Network Asic with Optical I/O

Wed, Mar 11, 2020 - 455 Words - 3 minutes

On 5 March Intel announced that is successfully integrated its 1.6 Tbps silicon photonics engine with a 12.8 Tbps Barefoot Tofino 2 ASIC. This switch uses optical fiber to the front panel ports instead of the usual copper tracks on the PCB (Printed Circuit Board) to QSFP28 front panel cages.

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The End of Moore's Law

Tue, Mar 19, 2019 - 945 Words - 5 minutes

For about half a century we have been living in a world where the speed of computers grew at an exponential rate. This is known as Moore's law, which is actually an observation of Gordon Moore that the number of transistors in an integrated circuit doubled approximately every two years. But today, that rate has almost levelled off. And Moore's law is not the only exponential that has come to its end. The same is true for Dennard scaling. In networking we are also hitting limits. We have reached the Shannon limit in optical communication. And in network ASIC design we reached the limit of serial bandwidth I/O. The next sections explore the current challenges and the final sections describe R&D that is exploring ways to overcome these challenges.

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